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Download Xilinx UG331 Spartan-3 Generation FPGA User Guide
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R Chapter 9: Using Carry and Arithmetic Logic . ASET ADD SSET D_OVFL D_C_OUT Q_OVFL Q_C_OUT OVFL C_OUT A[N:0] A_SIGNED S[P:0] D[P:0] Q[P:0] B_SIGNED B[M:0] BYPASS CE BYPASS C_IN CLK ACLR SCLR AINIT SINIT UG331_c11_18_073106 Figure 9-18: CORE Generator Adder/Subtractor Accumulator The CORE Generator system's Accumulator is similar to the Adder/Subtractor but with the registered output Q feeding back in the A input of the adder. Functions built using the Accumulator use the Spartan-3 generation carry logic. Comparator The CORE Generator system's Comparator function also takes advantage of the carry logic in implementation. Multiplier The CORE Generator system also includes a multiplier that can be targeted to either the carry logic or the dedicated 18 x 18 multipliers. The graphical interface for the Multiplier core includes the Multiplier Construction option. If Use LUTs is selected, the multiplier is built using the carry and MULT_AND logic. If Use 18 x 18 Multiplier Blocks is selected, the multiplier is built using the dedicated 18 x 18 multipliers. 296 www.xilinx.com Spartan-3 Generation FPGA User Guide UG331 (v1.5) January 21, 2009
