1
Download VR4181 specs - Delorie Software
Transcript
CHAPTER 15 POWER MANAGEMENT UNIT (PMU) 15.6.1 PMUINTREG (0x0B00 00A0) (1/2) Bit 15 14 13 12 11 10 9 8 Reserved Reserved Reserved GP WAKEUP CF_INT DCDST RTCINTR BATTINH R/W R R R R/W R/W R R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reserved SDRAM TIMOUT RST RTCRST RSTSW DMSRST BATTINTR POWER SWINTR R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Name Name R/W Bit Name Function 15 to 13 Reserved 0 is returned when read 12 GPWAKEUP GPIO interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 11 CF_INT CF_INT interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 10 DCDST DCD# pin state 1 : High level (inactive) 0 : Low level (active) 9 RTCINTR RTC alarm interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 8 BATTINH Battery low detection during activation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 7 Reserved Write 0 when write. 0 is returned when read. 6 SDRAM This bit determines whether the internal peripheral units are reset by RSTSW. This bit must be clear to 0 when EDO-DRAM is used. 1 : Reset (SDRAM data lost during RSTSW) 0 : Not reset (SDRAM data preserved during RSTSW) User’s Manual U14272EJ1V0UM00 331
