1
Download VR4181 specs - Delorie Software
Transcript
CHAPTER 27 MIPS III INSTRUCTION SET DETAILS BGEZAL 31 Branch on Greater than or Equal to Zero And Link 26 25 21 20 16 15 BGEZAL 0 REGIMM 000001 rs BGEZAL 10001 offset 6 5 5 16 Format: BGEZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16bit offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is placed in the link register, r31. If the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. General register rs may not be general register r31, because such an instruction is not restartable. An attempt to execute this instruction is not trapped, however. Operation: 32 T: target ← (offset15) || offset || 0 14 2 condition ← (GPR [rs]31 = 0) GPR [31] ← PC + 8 T+1: if condition then PC ← PC + target endif 64 T: target ← (offset15) || offset || 0 46 2 condition ← (GPR [rs]63 = 0) GPR [31] ← PC + 8 T+1: if condition then PC ← PC + target endif Exceptions: None User’s Manual U14272EJ1V0UM00 577
