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I N T R O D U C T I O N
T O
V I R T E X - I I
P R O
A A N D
I S E
o Up to two IBM® PowerPC™ RISC processor blocks
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Based on Virtex™-II FPGA technology
o Flexible logic resources, up to 125,136 Logic Cells
o SRAM-based in-system configuration
o Active Interconnect™ technology
o SelectRAM™ memory hierarchy
o Up to 556 Dedicated 18-bit x 18-bit multiplier blocks
o High-performance clock management circuitry
o SelectIO™-Ultra technology
o Digitally Controlled Impedance (DCI) I/O
1.2 PowerPC™ 405 Core
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Embedded 300+ MHz Harvard architecture core
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Low power consumption: 0.9 mW/MHz
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Five-stage data path pipeline
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Hardware multiply/divide unit
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Thirty-two 32-bit general purpose registers
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16 KB two-way set-associative instruction cache
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16 KB two-way set-associative data cache
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Memory Management Unit (MMU)
o 64-entry unified Translation Look-aside Buffers (TLB)
o Variable page sizes (1 KB to 16 MB)
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Dedicated on-chip memory (OCM) interface
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Supports IBM CoreConnect™ bus architecture
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Debug and trace support
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Timer facilities
1.3 RocketIO 3.125 Gbps Transceivers
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Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s
to 3.125 Gb/s (please reference the Xilinx datasheet for speed grade
limitations)
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80 Gb/s duplex data rate (16 channels)
DN6000K10SC User Guide
www.dinigroup.com
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