Download i960 Jx Microprocessor Developer`s Manual

DATA TYPES AND MEMORY ADDRESSING MODES
In cases where an instruction specifies a register number (and multiple, consecutive registers are
implied), the register number must be even when two registers are accessed (e.g., g0, g2) and an
integral multiple of four when three or four registers are accessed (e.g., g0, g4). When a register
reference for a source value is not properly aligned, the registers that the processor writes to are
undefined.
The i960 Jx processor does not require data alignment in external memory; the processor hardware
handles unaligned memory accesses automatically. Optionally, user software can configure the
processor to generate a fault on unaligned memory accesses.
2.1.6
Literals
The architecture defines a set of 32 literals that can be used as operands in many instructions.
These literals are ordinal (unsigned) values that range from 0 to 31 (5 bits). When a literal is used
as an operand, the processor expands it to 32 bits by adding leading zeros. When the instruction
requires an operand larger than 32 bits, the processor zero-extends the value to the operand size.
When a literal is used in an instruction that requires integer operands, the processor treats the
literal as a positive integer value.
2.2
BIT AND BYTE ORDERING IN MEMORY
All occurrences of numeric and non-numeric data types, except bits and bit fields, must start on a
byte boundary. Any data item occupying multiple bytes is stored as big endian or little endian. The
following sections further describe byte ordering.
2.2.1
Bit Ordering
Bits within bytes are numbered such that when the byte is viewed as a value, bit 0 is the least
significant bit and bit 7 is the most significant bit. For numeric values spanning several bytes, bit
numbers higher than 7 indicate successively higher bit numbers in bytes with higher addresses.
Unless otherwise noted, bits in illustrations in this manual are ordered such that the
higher-numbered bits are to the left.
2.2.2
Byte Ordering
The i960 Jx processor can be programmed to use little or big endian byte ordering for memory
accesses. Byte ordering refers to how data items larger than one byte are assembled:
•
For little endian byte order, the byte with the lowest address in a multi-byte data item has the
least significance.
•
For big endian byte order, the byte with the lowest address in a multi-byte data item has the
most significance.
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