Download Block Parameters
Transcript
Interleaver/De‐interleaver 7.1 • TREADY: TREADY for the Data Input Channel. Used by the Symbol Interleaver/De-interleaver to signal that it is ready to accept data. • FDO: Adds a data_tuser_fdo (First Data Out) output port. • RDY: Adds a data_tuser_rdy output port. • BLOCK_START: Adds a data_tuser_block_start output port. • BLOCK_END: Adds a data_tuser_block_end output port. Pipelining • Pipelining: Pipelines the underlying LogiCORE for Minimum, Medium, or Maximum performance Other parameters used by this block are explained in the topic Common Options in Block Parameter Dialog Boxes. LogiCORE™ Documentation LogiCORE IP Interleaver/De-interleaver v7.1 Vivado: Designing with System Generator UG958 (v2012.3) November 16, 2012 www.xilinx.com 197
Related documents
Block Parameters
UG638 - Xilinx
Vivado Design Suite Reference Guide: Model-Based DSP
EDK Processor
MATLAB SIMULINK HDL CODER - RELEASE NOTES User guide
MATLAB FIXED-POINT TOOLBOX - RELEASE NOTES User guide
Xilinx System Generator for DSP User Guide
BugHunter Pro and the VeriLogger Simulators
Simulation
System Generator for DSP User Guide
CIC Compiler v4.0 LogiCORE IP Product Guide (PG140)
A-126 Service Manual Seite/Page 10 6. Test
Xilinx System Generator for DSP User Guide (UG640)
Xilinx PG025 LogiCORE IP Reed-Solomon Encoder v8.0, Product
Xilinx V2.1 User's Manual