Download Block Parameters

Complex Multiplier 5.0
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Pass_A_TLAST: Pass the value of the a_tlast input port to the dout_tlast output port.
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Pass B_TLAST: Pass the value of the b_tlast input port to the dout_tlast output port.
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Pass CTRL_TLAST: Pass the value of the ctrl_tlast input port to the dout_tlast output
port.
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OR_all_TLASTS: Pass the logical OR of all the present TLAST input ports.
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AND_all_TLASTS: Pass the logical AND of all the present TLAST input ports.
Core Latency
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Latency Configuration
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Automatic: Block latency is automatically determined by System Generator by
pipelining the underlying LogiCORE for maximum performance.
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Manual: You can adjust the block latency specifying the minimum block latency.
Minimum Latency: Entry field for manually specifying the minimum block latency.
Control Signals
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ACLKEN: Enables the clock enable (aclken) pin on the core. All registers in the core are
enabled by this control signal.
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ARESETn: Active-low synchronous clear input that always takes priority over ACLKEN. A
minimum ARESETn active pulse of two cycles is required, since the signal is internally
registered for performance. A pulse of one cycle resets the core, but the response to
the pulse is not in the cycle immediately following.
Advanced tab
Block Icon Display
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Display shortened port names: On by default. When unchecked, dout_tvalid, for
example, becomes m_axis_dout_tvalid.
How to Migrate from Complex Multiplier 3.1 to Complex Multiplier 5.0
Design Description
This example shows how to migrate from the non-axi Complex Multiplier block to AXI4
Complex Multiplier block using the same or similar block parameters. Some of the
parameters between non-AXI4 and AXI4 versions might not be identical exactly due to
some changes in certain features and block interfaces.
Vivado: Designing with System Generator
UG958 (v2012.3) November 16, 2012
www.xilinx.com
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