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Download Altera UG-01080 User guide
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1-2 UG-01080 2015.01.19 Native Transceiver PHYs Figure 1-1: Transceiver PHY Top-Level Modules Transceiver PHY Avalon-MM Control & Status Embedded Controller To MAC Avalon-MM PHY Management S S M Read & Write Control & Status Registers Avalon-ST TX and RX PCS & PMA Control & Status Register Memory Map PMA PCS Customized functionality for: Rx Deserializer 10GBASE-R 10GBASE-KR 1G/10GBASE-R XAUI Interlaken PCI Express PIPE Altera Transceiver Reconfiguration Controller S Offset Cancellation Analog Settings M Avalon-MM master interface Reset Controller To HSSI Pins Tx Serializer PLL S CDR Avalon-MM slave interface Related Information • • • • • • 10GBASE-R PHY IP Core on page 3-1 Backplane Ethernet 10GBASE-KR PHY IP Core Overview 1G/10 Gbps Ethernet PHY IP Core on page 5-1 XAUI PHY IP Core on page 6-1 Interlaken PHY IP Core on page 7-1 PHY IP Core for PCI Express (PIPE) on page 8-1 Native Transceiver PHYs Each device family, beginning with Series V devices offers a separate Native PHY IP core to provide lowlevel access to the hardware. There are separate IP Cores for Arria V, Arria V GZ, Cyclone V, and Stratix V devices. The Native PHYs allow you to customize the transceiver settings to meet your requirements. You can also use the Native PHYs to dynamically reconfigure the PCS datapath. Depending on protocol mode selected, built-in rules validate the options you specify. The following figure illustrates the Stratix V Native PHY. Altera Corporation Introduction to the Protocol-Specific and Native Transceiver PHYs Send Feedback
