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Download Altera UG-01080 User guide
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14-32 UG-01080 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY Parameter Range Description Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_ fifo_pfull port. tx_10g_fifo_pfull is synchronous to coreclk. Enable tx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_ fifo_empty port. tx_10g_fifo_empty is pulse-stretched. It is asynchronous to coreclk and synchronous to tx_ clkout which is the read clock. Enable tx_10g_fifo_pempty port On/Off When you turn this option On, the 10G PCS includes the tx_10g_fifo_pempty port. Enable tx_10g_fifo_del port (10GBASE-R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_ fifo_del port. This signal is asserted when a word is deleted from the TX FIFO. This signal is only used for the 10GBASE-R protocol. Enable tx_10g_fifo_insert port (10GBASE-R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_ fifo_insert port. This signal is asserted when a word is inserted into the TX FIFO. This signal is only used for the 10GBASE-R protocol. 10G RX FIFO The RX FIFO is the interface between RX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. The following table describes the 10G RX FIFO parameters. Altera Corporation Arria V GZ Transceiver Native PHY IP Core Send Feedback
