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Download Altera UG-01080 User guide
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TOC-6 Altera Transceiver PHY IP Core User Guide Parameterizing the Custom PHY.............................................................................................................. 9-3 General Options Parameters.......................................................................................................... 9-3 Word Alignment Parameters......................................................................................................... 9-7 Rate Match FIFO Parameters......................................................................................................... 9-9 8B/10B Encoder and Decoder Parameters................................................................................. 9-10 Byte Order Parameters.................................................................................................................. 9-11 PLL Reconfiguration Parameters.................................................................................................9-14 Analog Parameters.........................................................................................................................9-16 Presets for Ethernet........................................................................................................................9-16 Interfaces..................................................................................................................................................... 9-19 Data Interfaces................................................................................................................................9-19 Clock Interface............................................................................................................................... 9-23 Optional Status Interface.............................................................................................................. 9-24 Optional Reset Control and Status Interface............................................................................. 9-26 Register Interface and Register Descriptions............................................................................. 9-27 Custom PHY IP Core Registers................................................................................................... 9-29 SDC Timing Constraints.............................................................................................................. 9-33 Dynamic Reconfiguration............................................................................................................ 9-33 Low Latency PHY IP Core.................................................................................10-1 Device Family Support..............................................................................................................................10-2 Performance and Resource Utilization...................................................................................................10-2 Parameterizing the Low Latency PHY....................................................................................................10-3 General Options Parameters.................................................................................................................... 10-4 Additional Options Parameters............................................................................................................... 10-7 PLL Reconfiguration Parameters...........................................................................................................10-10 Low Latency PHY Analog Parameters..................................................................................................10-12 Low Latency PHY Interfaces..................................................................................................................10-13 Low Latency PHY Data Interfaces.........................................................................................................10-13 Optional Status Interface........................................................................................................................ 10-15 Low Latency PHY Clock Interface........................................................................................................ 10-15 Optional Reset Control and Status Interface....................................................................................... 10-16 Register Interface and Register Descriptions....................................................................................... 10-17 Dynamic Reconfiguration...................................................................................................................... 10-19 SDC Timing Constraints........................................................................................................................ 10-20 Simulation Files and Example Testbench.............................................................................................10-21 Deterministic Latency PHY IP Core.................................................................11-1 Deterministic Latency Auto-Negotiation...............................................................................................11-2 Achieving Deterministic Latency............................................................................................................ 11-3 Deterministic Latency PHY Delay Estimation Logic............................................................................11-4 Deterministic Latency PHY Device Family Support............................................................................ 11-7 Parameterizing the Deterministic Latency PHY................................................................................... 11-8 General Options Parameters for Deterministic Latency PHY................................................ 11-8 Additional Options Parameters for Deterministic Latency PHY ........................................ 11-10 PLL Reconfiguration Parameters for Deterministic Latency PHY.......................................11-13 Deterministic Latency PHY Analog Parameters..................................................................... 11-15 Altera Corporation
