1
Download Altera UG-01080 User guide
Transcript
UG-01080 2015.01.19 RX PMA Parameters 13-9 The following table lists the best case latency for the most significant bit of a word for the RX deserializer for the PMA Direct datapath. PMA Direct mode is supported for Arria V GT, ST, and GZ devices only. Table 13-7: Latency for RX Deserialization in Arria V Devices FPGA Fabric Interface Width Arria V Latency in UI 8 bits 19 10 bits 23 16 bits 35 20 bits 43 64 bits 99 80 bits 123 The following table lists the best- case latency for the LSB of the TX serializer for all supported interface widths for the PMA Direct datapath. Table 13-8: Latency for TX Serialization n Arria V Devices FPGA Fabric Interface Width Arria V Latency in UI 8 bits 43 10 bits 53 16 bits 67 20 bits 83 64 bits 131 80 bits 163 The following table shows the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports. However, depending upon the interface width selected not all bits on the bus will be active. The following table shows which bits are active for each FPGA Fabric Interface Width selection. For example, if your interface is 16 bits, the active bits on the bus are [17:0] and [7:0] of the 80 bit bus. The non-active bits are tied to ground. Table 13-9: Active Bits for Each Fabric Interface Width FPGA Fabric Interface Width Bus Bits Used 8 bits [7:0] Arria V Transceiver Native PHY IP Core Send Feedback Altera Corporation
