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UG-01080
2015.01.19
10G PCS Parameters for Stratix V Native PHY
12-33
Table 12-25: 10G RX FIFO Parameters
Parameter
RX FIFO Mode
Range
Interlaken
clk_comp
phase_comp
register
RX FIFO full threshold
0-31
RX FIFO empty threshold
0-31
RX FIFO partially full threshold
0-31
RX FIFO partially empty threshold
0-31
Enable RX FIFO alignment word deletion
(Interlaken)
Stratix V Transceiver Native PHY IP Core
Send Feedback
On/Off
Description
Specifies one of the following 3 modes:
• interlaken : Select this mode for the
Interlaken protocol. To implement
the deskew process. In this mode the
FIFO acts as an elastic buffer. The
FIFO write clock can exceed the read
clock. Your implementation must
control the FIFO write (tx_
datavalid) by monitoring the FIFO
flags. The read enable is controlled
by the Interlaken Frame Generator.
• clk_comp : This mode compensates
for the clock difference between the
PLD clock (coreclkin) and
rxclkout. After block lock is
achieved, idle ordered set insertions
and deletions compensate for the
clock difference between RX PMA
clock and PLD clock up to ± 100
ppm. Use this mode for 10GBASE-R.
• phase_comp : This mode
compensates for the clock phase
difference between the PLD clock
(coreclkin) and rxclkout.
• register : The TX FIFO is bypassed.
rx_data and rx_data_valid are
registered at the FIFO output.
Specifies the full threshold for the 10G
PCS RX FIFO. The default value is 31.
Specifies the empty threshold for the
10G PCS RX FIFO. The default value is
0.
Specifies the partially full threshold for
the 10G PCS RX FIFO. The default
value is 23.
Specifies the partially empty threshold
for the 10G PCS RX FIFO.
When you turn this option On, all
alignment words (sync words),
including the first sync word, are
removed after frame synchronization is
achieved. If you enable this option, you
must also enable control word deletion.
Altera Corporation