Download Firmware development and intergration for ALICE TPC

169
•
VREG Module updated with new version from KIP.
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Timing warnings removed with correct constraints settings.
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Removed all "sensitivity list" warnings in Ethernet, jtag, vreg and I2C module.
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All controllable outputs to RCU (except dcs_ctrl[7:6] = "00") is set to high impedance if
output_enable_n = 1 is high.
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output_enable_n is set by bit 4 in ComStat register.
Version 2.6 (01.08.2006)
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RCU Communication Module:
o
RCU Flash interface rebuilt to match latest version of RCU support FPGA FW (v1.3).
o
Improved error-handling in Flash interface. Checks for RynBy line, as well as bit q(5) of
Flash-data.
o
Added Comstat(5) as DCS FW reset.
o
Changed rcu_data(15) in Flash mode to input f_rynBy.
o
Added a new generic variable that makes it possible to select the type of Flash of the RCU
Motherboard. BB = boot sector in the beginning, BT = boot sector at the end.
Version 2.61 (Trigger-OR)
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Pinning on DCS-RCU connector changed to match Trigger-OR board.
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Added sm_enable register that is enabled by writing to 0xBF01.
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Bus data width reduced to 16 bits. The remaining 16 bits are used for SelectMAP interface.
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SelectMAP interface can be accessed simultaneously as memory mapped interface.
Version 2.62 (BusyBox)
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Equal to v2.61 but with slightly different pinning on dcs-rcu (busy-logic) connector.
Version 2.7 (03.08.2007)
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Ethernet Module upgraded to increase speed of Ethernet link as described 40. This upgrade also means
updating the Kernel of the board.
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Minor bugs in v2.6x corrected related to the RCU master module.
Version 2.71 (Trigger-OR)
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Same as v2.61, but including the upgrades given in v2.7.
Version 2.72 (BusyBox)
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40
Same as v2.62, but including the upgrades given in v2.7.
http://frodo.nt.fh-koeln.de/~tkrawuts/update_howto/