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DN5000k10 Features, Overview and General Description
Synthesis and Emulation Issues
The QuartusII™ software from Altera is able to synthesize directly from
Verilog or VHDL code. However, third-party synthesis tools provide an
advantage: to create a memory block or multiplier, all you need to do is
describe them functionally, and the tool will infer the appropriate DSP and
RAM megafunctions for Quartus to place and route. On the other hand, if
you are using Quartus to synthesize, and you try to infer an M-RAM block
using a functional description, Quartus will attempt to route 200,000 LEs
as a memory array. So, if you don't have any other synthesis tool, you will
need to become familiar with Quartus megafunctions.
We have tried the following tools for synthesis:
Synplicity Synplify (http://www.synplicity.com/)
Synopsys FPGA Express (http://www.synopsys.com/)
Synopsys FPGA Compiler II
Exemplar LeonardoSpectrum
(http://www.exemplar.com/products/leonardospectrum.html)
Of the four listed here, we find that Synplicity offers the best performance, followed by Exemplar. The Synopsys products are not the easiest
products to use, and probably should be avoided until Synopsys decides
that they want to be in this market. It is generally not worth your time to
preserve your Synopsys ASIC compiler directives and scripts by using the
FPGA synthesis products from Synopsys. The time you save using Snopsys
products is offset by other hassles.
Synthesis
Notes
1. The FPGAs used on your DN5000k10 are EP1S80s in an F1508 package
(EP1S60s available on request). Unless you paid for a faster speed
grade, the –6 is what you will be getting.
2. Assuming you have a synthesis tool other than QuartusII, memories
are best implemented by describing them behaviorally in your RTL. All
four synthesis products are sophisticated enough to map your behavioral descriptions into the memory blocks. It is NOT necessary to
instantiate memories manually, unless you are synthesizing with
Quartus. Make sure, however, to check the report files to make sure
that your memories were implemented in memory blocks (if this is
possible). If input and output registers in your RTL don’t match the
behavior of the embedded memory blocks, the synthesis program
may not recognize what you intended, and give you arrays of LEs
instead.
3. Much to our surprise, the synthesis programs recognized RTL multiplier code and used the embedded multipliers without any trouble.
So, like the memories, RTL description of your multipliers is all that is
necessary unless you are synthesizing with Quartus. Make sure to
check the report files—multipliers that are implemented using logic
blocks (as opposed to the embedded memory blocks) take huge
amounts of FPGA resources.
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The DINI Group