Download Intel Xeon D-1540

EHCI Controller Registers (D29:F0)
Bit
15:08
Description
OC1Mapping Each bit position maps OC1 (EHCI 1) to a set of ports as follows:
EHCI 1: Map OC1
Bit:
Port:
15
X
14 13 12 11 10 9 8
X X X 3 2 1 0
It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
07:00
OC0 Mapping Each bit position maps OC0 (EHCI 1) to a set of ports as follows:
EHCI 1: Map OC0
Bit:
Port:
7
X
6
X
5 4 3 2 1 0
X X 3 2 1 0
It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin.
10.1.33
RMHWKCTL—RMH Wake Control Register
Address Offset:
7Eh
Default Value:
0000h
Function Level Reset: No
Bit
15:09
08
07:04
10.1.34
Attribute:
Size:
Power well:
R/W, RO
16 bits
Suspend
Description
Reserved
RMH Inherit EHCI Wake Control Settings -R/W:
0 = bits 2:0 of this register DO NOT reflect the appropriate bits of EHCI PORTSC0 bits 22:20.
1 = Bits 2:0 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20.
Reserved
03
RMH Upstream Wake on Device Resume Disable- R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a device
resume occurs on an enabled downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake when a
device resume occurs on an enabled downstream port
02
RMH Upstream Wake on OC Disable - R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when over-current
condition occurs downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake when overcurrent condition occurs downstream port
01
RMH Upstream Wake on Disconnect Disable - R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a disconnect
event occurs on a downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake when a
disconnect event occurs on a downstream port
00
RMH Upstream Wake on Connect Disable- R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a connect
event occurs on a downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake when a
connect event occurs on a downstream port
ACCESS_CNTL—Access Control Register (USB EHCI—
D29:F0)
Address Offset:
80h
Default Value:
00h
Function Level Reset: No
Bit
7:1
Attribute:
Size:
R/W
8 bits
Description
Reserved
Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
405