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SATA Controller Registers (D31:F2) 8 SATA Controller Registers (D31:F2) 8.1 PCI Configuration Registers (SATA–D31:F2) Note: Address locations that are not shown should be treated as Reserved. All of the SATA registers are in the core well. None of the registers can be locked. Table 8-1. Offset SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2) Mnemonic Register Name Default Attribute 00h–01h VID Vendor Identification 8086h RO 02h–03h DID Device Identification See register description RO 04h–05h PCICMD PCI Command 0000h R/W, RO 06h–07h PCISTS PCI Status 02B0h R/WC, RO 08h RID Revision Identification See register description RO 09h PI Programming Interface See register description See register description 0Ah SCC Sub Class Code See register description See register description 0Bh BCC Base Class Code 01h RO 0Dh PMLT 0Eh HTYPE Primary Master Latency Timer 00h RO Header Type 00h RO 10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO 14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO 18h–1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO 1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO 20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO 24h–27h ABAR / SIDPBA AHCI Base Address / SATA Index Data Pair Base Address See register description See register description 2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO 2Eh–2Fh SID Subsystem Identification 0000h R/WO 34h CAP Capabilities Pointer 80h RO 3Ch INT_LN Interrupt Line 00h R/W 3Dh INT_PN Interrupt Pin See register description RO 40h–41h IDE_TIM Primary IDE Timing 0000h R/W 42h–43h IDE_TIM Secondary IDE Timing 0000h R/W 44h SIDETIM Slave IDE Timing 00h R/W 48h SDMA_CNT Synchronous DMA Control 00h R/W 4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W 54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W PCI Power Management Capability Identification See register description RO 70h–71h PID Intel® Xeon® Processor D-1500 Product Family Datasheet - Volume 1 of 4: Integrated Platform Controller Hub March 2015 323
