Download Intel Xeon D-1540

SATA Controller Registers (D31:F2)
8.1.20
INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset:
3Ch
Default Value:
00h
Function Level Reset:No
Bit
7:0
8.1.21
R/W
8 bits
Description
Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the
interrupt pin is connected to.
Interrupt Line register is not reset by FLR.
INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset:
Default Value:
3Dh
See Register Description
Bit
7:0
8.1.22
Attribute:
Size:
Attribute:
Size:
RO
8 bits
Description
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config Registers:Offset
3100h:bits 11:8).
IDE_TIM—IDE Timing Register (SATA–D31:F2)
Address Offset:
Default Value:
Primary:
40h–41h
Secondary: 42h–43h
0000h
Attribute:
R/W
Size:
16 bits
Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These
bits have no effect on hardware.
Bit
15
14:12
11:10
9:0
8.1.23
Description
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to decode the associated Command
Block (1F0–1F7h for primary,
170–177h for secondary, or their native mode BAR equivalents) and Control Block (3F6h for
primary, 376h for secondary, or their native mode BAR equivalents).
This bit effects the IDE decode ranges for both legacy and native-mode decoding.
IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
Reserved
IDE_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
Address Offset:
Default Value:
Note:
44h
00h
Attribute:
Size:
R/W
8 bits
This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit
Description
7:0
SIDETIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
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